The present invention relates to integrated circuits and, more particularly, to integrated circuit memory devices. A major objective of the present invention is to provide for greater flexibility in integrated circuit memory design to meet package size constraints.
Recent technological progress has been closely identified with the development of high-speed, high-density integrated circuits. Among the most prevalent of integrated circuit devices are random access memories (RAMs). RAMs are typically divided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). DRAMs have the advantages of relatively low cost and relatively high density, but require refresh cycles that incur speed and power penalties. SRAMs are favored where memory access times must be kept to a minimum. An increasingly common computer architecture uses high-density DRAM memory for bulk memory and SRAM as cache memory to speed access to the most commonly used operations and data. SRAMs also have relatively low power requirements and are commonly used in battery powered units, including portable computers.
A conventional SRAM architecture includes an array of memory cells arranged in rows and columns. Data is communicated to and from the memory device via data ports. Cells are selected as a function of address codes received at address inputs. Read and write operations are selected at control inputs. In addition, power and ground, for example, nominal 5 V and 0 V, respectively, are supplied at respective terminals. An address decoder transforms received address codes into control signals that implement the requested cell selection. The address decoder transmits signals along word lines causing cells in a cell row to be coupled to respective true and false bit lines of a selected cell column. Some recent devices use divided word line architectures that divide the cell array into separately addressable blocks. This reduces capacitive loading by decreasing the number of cells in a cell row sharing a common row-select line. The address decoder also transmits signals to column pass gates or column transmission gates to couple selected bit lines to respective sense amplifiers and thence to the data ports.
SRAM designers, along with the designers of other memory types, are faced with competing demands for more advanced devices and for devices that are compatible with existing standards. For example, there is a demand for devices with greater memory capacity that fit into industry standard package configurations. If a memory device is incorporated within a novel package, it is less likely to be retrofit into existing systems and into systems already well along their design path. In addition, many systems builders are reluctant to depend on a single source, especially for memory devices, so they will not accept a new package until other manufacturers adopt it as a standard. Standardization of a new package configuration requires agreement between fierce industry competitors. Standards continue to evolve, but the process is time-consuming and its outcome is often uncertain. Therefore, if a new device can be incorporated into an accepted standard package, its acceptance in the marketplace is more easily assured.
However, the constraints imposed by standard packages can be burdensome. Memory devices have generally evolved by factors of four. For example, common SRAM devices have included 1024-bit (1 kilobit=1k), 4k, 16k, 64k, 256k, and 1024k (1 megabit=1M) memories. Binary addressing schemes favor memories in which the number of addressable cells is a power of two. For a rectangular array of cells, this requires that the number of cell rows is a power of two, and that the number of cell columns is a power of two. Thus, a 64k=2.sup.16 memory can have 256=2.sup.8 cell rows and 256 cell columns. When processing technology permits denser memory arrays, the tendency is to double the number of cell rows and double the number of cell columns. Thus, the next generation device would be 512.times.512, which yields a 256k-bit memory.
When processing technology provides for 50% linear reduction in cell pitch, the next generation can be arranged in roughly the same area as the previous generation. However, pitch reductions are usually less dramatic. Furthermore, pitch reductions can be offset by increasing routing complexity and increased architectural complexity--e.g., the more sophisticated block decode logic used in bigger memory devices. Hence, while processing technology provides some savings in device area, memories with larger capacity generally require more area.
Thus, a device with four times as many cells fabricated using a process providing a 25% reduction in feature size could require an array 50% longer and 50% wider than the previous generation memory. When no suitable standard package is available, some adjustments must be made. Sometimes, a standard package can accommodate a change in one dimension and not the other. In this case, a designer could limit the number of cell rows and cell columns in one dimension while taking advantage of the latitude in the other dimension. Thus, a 512.times.256 memory using the advanced technology could fit a package; however, the resulting device would have a 128k memory size, which is non-standard. If sufficient latitude in one dimension were available, a 256k memory could be arranged as 1024.times.256 cells. While these accommodations can be made, the number of options is still quite limited.
As an extreme example, a package that can accommodate a maximum of 500.times.500=250,000 cells, accommodates a maximum of 256.times.256=64k binary-addressable cells. It is difficult to optimize memory capacity and yet conform to the dimensional constraints of standard packages.
The provision of redundant cells in memory devices modifies the basically binary character of memory array dimensions, but only slightly. The more cells in a memory device, the more likely it is that at least one of these cells will be defective. Extra cells can be manufactured on a device to substitute for cells found during testing to be defective. A laser can be used to reroute addressing signals to the substitute cells. The substitute cells can be arranged as additional cell columns or cell rows. In a divided word or other block architecture, the substituted cells can be arranged in separate blocks, or as additional rows or columns in blocks containing the main cells.
Generally, redundant blocks are more conveniently implemented than are redundant cell rows or redundant cell columns in each block. However, implementation of redundant blocks in a conventional divided word architecture requires one redundant block for each block row or one redundant block for each block column. Generally, this requirement results in a greater level of redundancy than is required, thus wasting valuable area on an integrated circuit.
To permit substitution of any of the main cells without drastically increasing addressing complexity, substitution is on a row-by-row, column-by-column or block-by-block basis. Even if only one cell is defective, its entire block, cell row, cell column, block row or block column will be replaced. To permit any cell to be replaced, redundant blocks, columns and rows are arranged to extend either the entire length or the entire width of the memory array. It is not necessary to provide redundancy over both the full width and the full length. Therefore, redundant cells can be added so that the length of the array is increased, but not the width; alternatively, the redundant cells can be added so that the width of the array is increased, but not the length. The choice can be made to conform to packing constraints.
Accordingly, a memory device incorporating redundancy will not generally have an array that has a binary power of cells. Such a device could have a semi-binary array that is 2.sup.m .multidot.(2.sup.n +r), where m, n and r are positive integers. For example, four percent redundancy can be provided in a 256.times.266 array. One dimension of the array is binary and the other is near binary. This would still fall far short of efficient utilization of the 250,000 cell capacity for the package in the above example.
Thus, providing redundancy can use some of the area otherwise wasted when array dimensions conform to packaging constraints. However, this saving is limited. Redundancy requirements arise primarily from yield considerations. Rerouting complexities and the law of diminishing returns limit the amount of useful redundancy. The basic difficulty of efficiently accommodating newer, higher-capacity memories in standard packages remains.